The inventive concept relates generally to memory devices, memory systems and methods of operating same. More particularly, the inventive concept relates to nonvolatile memory devices capable of storing multiple data bits per memory cell, memory systems incorporating such nonvolatile memory devices and methods of operating same.
Semiconductor, nonvolatile memory devices have become an important and staple component in contemporary memory systems, such as those typically used in computers, smartphones and other portable, personal electronic devices. Nonvolatile memory devices include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM) such as flash memory, Phase-change Random Access Memory (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM).
With advancement in semiconductor fabrication technologies, nonvolatile memory cells are increasingly capable of storing multiple data bits. Memory cells configured to store only a single data bit are referred to as single-level memory cells or SLC, where the value of the single stored bit may be discriminated using a single verification voltage. Memory cells configured to store two data bits are referred to as multi-level memory cells or MLC, where the respective values of the two stored bits may be discriminated using three verification voltages. Memory cells configured to store three data bits are referred to as tri-level memory cells or TLC, where the respective values of the three stored bits may be discriminated using seven verification voltages, and memory cells configured to store four data bits are referred to as quad-level memory cells or QLC, where the respective values of the four stored bits may be discriminated using fifteen verification voltages.
From these examples, it is clear that as the number of data bits stored in each memory cell incrementally increases, the number of verification voltages required to discriminate between the respective data states increases exponentially, along with the number of possible data states to which the memory cell may be programmed. In addition, each data-state verification operation—that uses a corresponding verification voltage—requires the execution of a “dump operation”. During a dump operation “write data” having being programmed to selected memory cell(s) of a memory cell array, and thereafter being verified for programming accuracy by a following verification operation, must be dumped from page buffer latches so that a next data-state verification operation may be performed.
The execution of multiple dump operations (e.g., potentially seven successive dump operations during programming of a TLC or fifteen successive dump operations during programming of a QLC) takes a considerable amount of time. Thus, as the number of stored bits per memory cell increases, the time required to verify programming of the memory cell increases in an exponentially related manner as more and more data states must be verified using more and more verification voltages and corresponding dump operations.